1. Field of The Invention
The present invention relates to a data processing system, and more particularly to such a kind of system including separate units for processing and executing instructions. These units communicate with a bus and are arranged to operate synchronously in accordance with microprogrammed control.
2. Description of the Prior Art
In order to increase the speed of processing and executing instructions, it is known in the art to provide separate instruction processing and execution units which are operated under microprogrammed control. These separate units are operatively coupled via a bus in a manner to operate in synchronism with each other. The instruction processing unit is provided with a plurality of microinstruction routines, and successively fetches instructions from a main memory and interprets each instruction under the control of the corresponding sequence of microinstructions. The execution unit is also provided with a plurality of microinstruction routines, and, executes, with microprogrammed control, the instruction in accordance with the result(s) obtained at the instruction processing unit, and, at the same time, the instruction processing unit fetches and implements the next instruction.
During the concurrent, synchronous implementations of the separate units, various information or data paths are formed depending on the microinstructions. In order to prevent the separate units from using the same bus at the same time, a bus utilization control technique has been proposed. In this specification, by definition, such a technique is termed "bus utiization priority control". In accordance with the prior art bus utilization priority control, each unit desiring to use the bus sends a bus utilization request to a bus arbitration means and is allowed to access the bus only when receiving a permission or acknowledgement from the bus arbitration means. In the event that the bus arbitration means receives a request from more than two units at the same time, the means determines the priority of the bus utilization. If the above-mentioned bus utilization priority control is not provided, there is a possibility that the separate units use the same bus concurrently. For example, two registers of the execution unit may communicate data using the bus at the same time when the instruction processing unit employs the same bus. One known practice for overcoming the above problem is to provide an additional bus which serves to transfer the data between the two registers whereby the concurrent use of the same bus can be avoided. The provision of the additional bus requires multiplexers for selectively switching over the registers to one of the two buses, and hence increases the number of parts with the attendant disadvantage of hardware complexity, and increases design difficulties especially where available parts space is limited.